1 ? fn3121.8 hi-200, hi-201 dual/quad spst, cmos analog switches hi-200/hi-201 (dual/quad) are monolithic devices comprising independently selectable spst swit ches which feature fast switching speeds (hi-200 240ns, and hi-201 185ns) combined with low power dissipation (15mw at 25 o c). each switch provides low ?on? resist ance operation for input signal voltage up to the supply rails and for signal current up to 80ma. rugged di constructi on eliminates latch-up and substrate scr failure modes. all devices provide break-before-make switching and are ttl and cmos compatible for maximum application versatility. hi-200/hi-201 are ideal components for use in high frequency analog switching. typical applications include signal path switching, sample and hold circuit, digital filters, and operational amplifier gain switching networks. features ? pb-free available (rohs compliant) ? analog voltage range . . . . . . . . . . . . . . . . . . . . . . . 15v ? analog current range . . . . . . . . . . . . . . . . . . . . . . . 80ma ? turn-on time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240ns ?low r on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ? ? low power dissipation. . . . . . . . . . . . . . . . . . . . . . .15mw ? ttl/cmos compatible applications ? high frequency analog switching ? sample and hold circuits ? digital filters ? operational amplifier gain switching networks functional diagram ordering information part number temp. range (c) package pkg. dwg. # HI3-0200-5Z (note) 0 to 75 14 ld pdip* (pb-free) e14.3 hi1-0201-2 -55 to 125 16 ld cerdip f16.3 hi1-0201-4 -25 to 85 16 ld cerdip f16.3 hi1-0201-5 0 to 75 16 ld cerdip f16.3 hi3-0201-5 0 to 75 16 ld pdip e16.3 hi3-0201-5z (note) 0 to 75 16 ld pdip* (pb-free) e16.3 hi4p0201-5 0 to 75 20 ld plcc n20.35 hi4p0201-5z (note) 0 to 75 20 ld plcc (pb-free) n20.35 hi9p0201-5 0 to 75 16 ld soic m16.15 hi9p0201-5z (note) 0 to 75 16 ld soic (pb-free) m16.15 hi9p0201-9 -40 to 85 16 ld soic m16.15 hi9p0201-9z (note) -40 to 85 16 ld soic (pb-free) m16.15 *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate ter- mination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or ex- ceed the pb-free requirements of ipc/jedec j std-020. pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. truth table logic hi-200 hi-201 0onon 1offoff reference, level shifter, and driver gate switch cell source drain output logic input v+ v ref v- input gate data sheet april 6, 2005 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1999, 2001, 2004, 2005. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn3121.8 april 6, 2005 pinouts (switches shown for logic ?1? input) hi-200 (pdip) top view hi-201 (cerdip, pdip, soic) top view hi-201 (plcc) top view a 2 nc gnd nc in2 out2 v- a 1 nc v+ nc in1 out1 v ref 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 1 out1 in1 v- gnd in4 a 4 out4 a 2 in2 v+ v ref in3 out3 a 3 out2 in1 v- nc gnd in4 out1 a1 nc a2 out2 out4 a4 nc a3 out3 in2 v+ nc v ref in3 4 5 6 7 8 10 11 12 13 9 3212019 16 17 18 15 14 schematic diagrams ttl/cmos reference circuit v ref cell hi-200 ttl/cmos reference circuit v ref cell hi-201 v+ gnd r 2 5k m p13 q p1 q n1 r 3 24.2k r 4 5.4k r 5 7.9k r 6 300 q p2 q p3 q p5 q p4 q n4 q n2 m n14 m n15 m n16 m n17 v- gnd r 7 100k v ll to p 2 v ref d 3 v+ gnd r 2 5k m p13 q p1 q n1 r 3 24.2k r 4 5.4k r 5 7.9k r 6 600 q p2 q p3 q p5 q p4 q n4 q n2 m n14 m n15 m n16 m n17 v- gnd r 7 100k v ll to p 2 v ref d 3 m p14 q n3 q p6 hi-200, hi-201
3 fn3121.8 april 6, 2005 switch cell digital input buffer and level shifter schematic diagrams (continued) a? input a ? v+ q p11 q n12 q n13 v- q p12 q n11 output q p3 q p1 q n1 to v ll to v ref q p2 q n2 200 ? d 1 d 2 v- a v+ q p4 q p5 q n6 q p7 q p6 q n7 q n5 q n4 q n3 v- v+ q p8 q p9 q p10 q n8 q n9 q n10 a? a ? hi-200, hi-201
4 fn3121.8 april 6, 2005 absolute maximum rati ngs thermal information supply voltage (v+ to v-) . . . . . . . . . . . . . . . . . . . . . . . . 44v ( 22) v ref to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v, -5v digital input voltage. . . . . . . . . . . . . . . . . . . . . . (v+) +4v to (v-) -4v analog input voltage (one switch) . . . . . . . . . . (v+) +2v to (v-) -2v operating conditions temperature ranges hi-201-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c hi-201-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c hi-200-5, hi-201-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c hi-201-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . . 75 20 plcc package. . . . . . . . . . . . . . . . . . . 80 n/a pdip package* . . . . . . . . . . . . . . . . . . 95 n/a soic package . . . . . . . . . . . . . . . . . . . 110 n/a maximum storage temperature . . . . . . . . . . . . . . . -65 o c to 150 o c maximum junction temperature (her metic packages). . . . . 175 o c maximum junction temperature (plastic packages) . . . . . . 150 o c maximum lead temperature (soldering, 10s) . . . . . . . . . . . 300 o c (plcc and soic - lead tips only) *pb-free pdips can be used for through hole wave solder process- ing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications supplies = +15v, -15v; v ref = open; v ah (logic level high) = 2.4v, val (logic level low) = 0.8v parameter test conditions temp ( o c) -2 -4, -5, -9 units min typ max min typ max dynamic characteristics switch on time, t on hi-200 25 - 240 500 - 240 - ns hi-201 25 - 185 500 - 185 - ns full - 1000 - - 1000 - ns switch off time, t off hi-200 25 - 330 500 - 500 - ns hi-201 25 - 220 500 - 220 - ns full - 1000 - - 1000 - ns off isolation (note 4) hi-200 25 - 70 - - 70 - db hi-201 25 - 80 - - 80 - db input switch capacitance, c s(off) 25 - 5.5 - - 5.5 - pf output switch capacitance, c d(off) 25 - 5.5 - - 5.5 - pf output switch capacitance, c d(on) 25 - 11 - - 11 - pf digital input capacitance, c a 25 - 5 - - 5 - pf drain-to-source capacitance, c ds(off) 25 - 0.5 - - 0.5 - pf digital input characteristics input low threshold, v al full - - 0.8 - - 0.8 v input high threshold, v ah full 2.4 - - 2.4 - - v input leakage current (high or low), i a (note 3) full - - 1.0 - - 1.0 a analog switch characteristics analog signal range, v s full -15 - +15 -15 - +15 v on resistance, r on (note 2) 25 - 55 70 - 55 80 ? full - 80 100 - 72 100 ? hi-200, hi-201
5 fn3121.8 april 6, 2005 off input leakage current, i s(off) (note 6) 25 - 1 5 - 1 50 na hi-200 full - 100 500 - 10 500 na hi-201 25 - 2 5 - 2 50 na full - - 500 - - 250 na off output leakage current, i d(off) (note 6) 25 - 1 5 - 1 50 na hi-200 full - 100 500 - 10 500 na hi-201 25 - 2 5 - 2 50 na full - 35 500 - 35 250 na on leakage current, i d(on) (note 6) 25 - 1 5 - 1 50 na hi-200 full - 100 500 - 10 500 na hi-201 25 - 2 5 - 2 50 na full - - 500 - - 250 na power supply characteristics (note 5) power dissipation, p d 25 - 15 - - 15 - mw full - - 60 - - 60 mw current, i+ 25 - 0.5 - - 0.5 - ma full - - 2.0 - - 2.0 ma current, i- 25 - 0.5 - - 0.5 - ma full - - 2.0 - - 2.0 ma notes: 2. v out = 10v, i out = 1ma. 3. digital inputs are mos gates: typical leakage is < 1na. 4. v a = 5v, r l = 1k ? , c l = 10pf, v s = 3v rms , f = 100khz. 5. v a = +3v or v a = 0v for both switches. 6. refer to leakage current measurements (figure 2). electrical specifications supplies = +15v, -15v; v ref = open; v ah (logic level high) = 2.4v, val (logic level low) = 0.8v (continued) parameter test conditions temp ( o c) -2 -4, -5, -9 units min typ max min typ max test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v and v ref = open figure 1a. on resistance test circuit v 2 1ma in out v in r on 2 v 1ma ------------ - = hi-200, hi-201
6 fn3121.8 april 6, 2005 figure 1b. on resistance vs temperature figure 1c. hi-200 on resistance vs analog signal level figure 1. on resistance figure 2a. leakage current vs temperature figure 2b. off leakage current test circuit figure 2c. on leakage current test circuit figure 2. leakage currents figure 3a. switch current vs voltage figure 3b. test circuit figure 3. switch current test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v and v ref = open (continued) 80 70 60 50 40 30 20 10 0 -25 -50 0 25 50 75 100 125 on resistance ( ? ) temperature ( o c) v in = 0v 100 50 0 -15 -10 -5 0 5 10 15 analog signal level (v) on resistance ( ? ) v+ = +12.5v v- = -12.5v v+ = +10v v- = -10v v+ = +15v v- = -15v 100 10 1.0 0.1 current (na) 25 50 75 100 125 temperature ( o c) i d(on) i s(off) / i d(off) in out a a 14v 14v + i d(off) i s(off) in out 14v a i d(on) 90 80 70 60 50 40 30 20 10 0 0 1234 567 voltage across switch ( v) switch current (ma) in out hi-201 i v in hi-200, hi-201
7 fn3121.8 april 6, 2005 figure 4a. measurement points v a = 0 to 4v vertical: 2v/div. horizontal: 100ns/div. figure 4b. waveforms with ttl compatible logic input v a = 0 to 15v vertical: 5v/div. horizontal: 100ns/div. figure 4c. waveforms with cmos compatible logic input figure 4. switch t on and t off figure 5. hi-201 off isolation vs frequency for more information see application notes an520, an521, an531, an532 and an557. test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v and v ref = open (continued) digital input switch output v ah = 4v 50% v al = 0v 80% t off t on 50% 0v 80% v a output output v a 140 120 100 80 60 40 20 0 100hz 1khz 10khz 100khz 1mhz frequency (hz) off isolation (db) r l = 1k ? hi-200, hi-201
8 fn3121.8 april 6, 2005 application information single supply operation the switch operation of t he hi-200/201 is dependent upon an internally generated s witching threshold voltage optimized for 15v power supplies. the hi-200/201 does not provide the necessary internal switching threshold in a single supply system. theref ore, if single supply operation is required, the hi-300 series of switches is recommended. the hi-300 series will remain operational to a minimum +5v single supply. switch performance will degrade as power supply voltage is reduced from optimum levels ( 15v). so it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will m eet the requirements of the application. for further information see application notes an520, an557, an1033 and an1034. hi-200, hi-201
9 fn3121.8 april 6, 2005 die characteristics metallization: type: cual thickness: 16k ? 2k ? passivation: type: nitride over silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2k ? worst case current density: 2 x 10 5 a/cm 2 at 25ma metallization mask layout hi-200 v- v ref in 1 out 1 4 5 6 7 8 3 gnd a 2 a 1 v+ 9 10 1 2 in 2 out 2 hi-200, hi-201
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3121.8 april 6, 2005 die characteristics metallization: type: cual thickness: 16k ? 2k ? passivation: type: nitride over silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2k ? worst case current density: 2 x 10 5 a/cm 2 at 25ma metallization mask layout hi-201 a 1 a 2 in 1 a 4 a 3 out 2 out 3 out 1 v- gnd in 4 out 4 in 2 v+ v ref in 3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 hi-200, hi-201
|
